The present invention relates to nonvolatile semiconductor memory cells. More particularly, the invention relates to a nonvolatile memory cell which is programmable and/or erasable by field emission.
Conventional nonvolatile memory cells include EPROM, Flash and EEPROM cells. EPROM cells are electrically programmed by moving electrons onto the cells floating gate via hot electron injection, and optically erased (removing electrons from the floating gate) by exposure of the cell to UV radiation. EEPROM cells are both electrically programmed and electrically erased by moving electrons on and off the cell's floating gate via Fowler-Nordheim tunneling. Flash cells have elements of both EPROMs and EEPROMs: they are electrically programmed by hot electron injection and electrically erased by Fowler-Nordheim tunneling. Each of these memory cells have particular applications for which they are best suited.
EEPROM cells have the advantages that they need not be exposed to UV radiation for erasure, and they do not require the cell circuitry necessary for generating fields sufficient for hot electron injection. Therefore, EEPROMs are preferred in applications where these requirements would make it impractical or impossible to use an EPROM or FLASH cell.
FIGS. 1A shows a perspective view of a typical EEPROM cell. The cell 30 is a single polysilicon EEPROM cell. As such, it does not have a polysilicon control gate, but instead has a heavily doped diffusion region in the cell's substrate which is capacitively coupled to its floating gate. The cell 30 includes a single polysilicon floating gate structure 32 which performs three functions. At a first end, a tunnel extension 34 of floating gate 32 acts as an electrode in the two terminal device used for tunneling electrons from a heavily doped N.sup.+ implant 35 (also referred to as a programming Memory Diffusion or MD) through a tunnel oxide 36 (often about 80 .ANG. thick) onto floating gate structure 32. At the other end of this floating gate, a wide area plate 38 is employed as one electrode of a capacitor enabling the floating gate 32 to be raised to a high voltage (e.g., about 6 to 11 volts) by capacitively coupling a programming voltage (e.g., about 9 to 13 volts) from a second electrode 40 (heavily doped N+ silicon, referred to herein as a control gate memory diffusion) through an oxide 42 (often about 180 .ANG. thick). Between these two ends is a section of polysilicon that forms the gate 44 of a read transistor (N2).
The read transistor (N2) is connected in series with a word line transistor (N1) having a gate 46 forming part of a word line (also referred to as a row line) 31. The read and word line transistors separate a sense amp negative (-) input 48 (a source line) from a sense amp positive (+) input 50 (a drain line). Charging the floating gate 32 by tunneling electrons onto it (through tunnel oxide 36) raises the threshold voltage of the read transistor (EEPROM cell 30 is programmed). This shuts off the channel between the sense amp inputs, even when the adjacent word line transistor is turned on. Tunneling electrons off the floating gate 32 reduces the read transistor threshold voltage to negative values, effectively turning this device on (EEPROM cell 30 is erased). The word line transistor in series then controls the signal path between the two sense amp inputs 48 and 50.
The EEPROM cell is programmed or erased by charging or discharging, respectively, the floating gate 32. In order to tunnel electrons onto floating gate 32, a high voltage must be applied to the control gate memory diffusion 40. At the same time, the write column 56 is grounded and the write column transistor (N3) is turned on by, for example, selecting the row line 31 with, for example, 5 volts. The sense amp (-) input 48 can be biased from about 5 volts to a high voltage to assist tunneling electrons onto the floating gate 32. The voltage on the control gate memory diffusion 40 is capacitively coupled to the floating gate 32 as is the sense amp (-) input 48 voltage. The resulting positive voltage on floating gate 32 is sufficient to cause tunneling onto floating gate 32 through the tunnel oxide 36 where it intersects the floating gate (the tunnel oxide window 36a (shaded)), thereby programming the EEPROM cell 30.
In order to tunnel electrons off floating gate 32, a high voltage must be applied to memory diffusion 35 while ground is applied to the second heavily doped N+ implant (control gate memory diffusion) 40 which underlies and is capacitively coupled to the wide area plate 38. During this process, ground is also applied to sense amp (-) input 48. The application of high voltage to memory diffusion 35 is accomplished through a write column 56 and a write column select transistor (N3) including (i) a diffusion region 54 conductively connected to write column 56 for data input, (ii) a source/drain diffusion 58 electrically connected to memory diffusion 35, and (iii) a gate electrode 60, which is part of row line 31. When a sufficient potential is applied to the gate 60 of the write column select transistor through row line 31 while a write signal is applied through write column 56, electrons can tunnel off of the floating gate 32 to erase the EEPROM cell.
FIG. 1B provides additional detail on the structure of the programming and erasing portion of a typical conventional EEPROM cell 100. This cross-sectional side view shows a substrate 102, typically composed of silicon, which contains a memory diffusion region 103. Overlying the substrate 102 is a dielectric layer 104 (typically composed of a relatively thin tunnel window region within a relatively thicker field of gate oxide (not shown)). A floating gate 106, typically composed of polysilicon, overlies the dielectric layer 104. The floating gate 106 is capacitively coupled to a control gate 110 through an interlayer dielectric 108. The control gate memory diffusion (40, FIG. 1A) is not visible in this depiction of the cell.
A further description of a typical EEPROM cell and its functional elements is available the publication "EPM7032 Process, Assembly, and Reliability Information Package" available from Altera Corporation of San Jose Calif. That document is incorporated herein by reference for all purposes.
Despite the EEPROM's advantages, there are certain drawbacks to its use. For instance, the EEPROM tunnel dielectric window is subject to charge retention problems arising from stress-induced leakage current (SILC) through the tunnel dielectric caused by cycling of the cell. This current leakage through the tunnel window on or off the floating gate affects the reliability of the cell. Also, while the EEPROM does not require a voltage path sufficiently high for hot electron injection, as in EPROM and FLASH cells, the voltage necessary for Fowler-Nordheim tunneling requires a high voltage path relative to normal cell operating voltages. This high voltage path requirement has two effects. The first is that it complicates circuit design. The second is that in order to generate the voltage necessary for Fowler-Nordheim tunneling, a large area of the basic cell is required to couple the control gate voltage on to the floating gate.
The large voltage coupling area requirement in turn imposes limits on the minimum die size of any product that utilizes EEPROM. EEPROM cells have an additional limitation that impacts design shrinks: There is a limit to how thin an EEPROM tunnel dielectric can be scaled due to enhanced charge retention problems arising, both from increased SILC, as well as direct tunneling. Therefore, both voltage coupling and tunnel window requirements limit the extent to which EEPROMs can be scaled as device sizes decrease.
Further, EEPROM cells have relatively iona, programming and erasure times, typically of about 40 ms, depending upon charge density. As a result, EEPROM cells are generally unsuitable for disk storage memory applications.
Accordingly, there is a need for alternative nonvolatile memory devices without the limitations of a conventional EEPROM.